netgen doesn't handle attributes correctly or escapes inside escapes.

[d-m-bailey]

Netgen 1.5.253

Sky130 MPW-4 Slot-029 coriolis_test_soc_-_mpw4

1. (* ... *) denotes attributes in verilog that various tools can use as needed. In netgen, they should probably be treated as comments. This verilog

/* Generated by Yosys 0.12+1 (git sha1 0417528ff, clang 13.0.0 -fPIC -Os) */

(* \amaranth.hierarchy  = "user_project_core_lambdasoc" *)
(* top =  1  *)
(* generator = "Amaranth" *)
(* src = "build/sky130/top.v:22213.1-22612.10" *)
module user_project_core_lambdasoc_cts(io_out, io_oeb, io_in, vccd1, vssd1);

yields

Expected to find instance pin block but got "="
Expected to find end of instance but got ""user_project_core_lambdasoc""
line number 3 = '(* \amaranth.hierarchy  = "user_project_core_lambdasoc" *)'
Warning:  Cell (* has no pins
Creating placeholder cell definition for module (*.
Note:  Implicit pin (no pins) in instance \amaranth.hierarchy  of (* in cell user_project_core_lambdasoc.v
Expected to find instance pin block but got "top"
Expected to find end of instance but got "="
line number 4 = '(* top =  1  *)'
Warning:  Cell *) has no pins
Creating placeholder cell definition for module *).
Note:  Implicit pin (no pins) in instance (* of *) in cell user_project_core_lambdasoc.v
Expected to find instance pin block but got "(*"
Expected to find end of instance but got "generator"
...

2. Removing the attributes. Uncovers another problem.

Badly formed subcircuit pin line at "[0]"
Expected to find end of instance but got ")"
line number 54517 = '  );'
Error:  Verilog backslash-escaped name does not end with a space.

Looking at line 54517

  nand2_x0 \$abc$109383$auto$blifparse.cc:381:parse_blif$110323  ( .vss(vssd1), .vdd(vccd1),
    .i0(\$abc$109383$new_n15674_ ),
    .i1(\$abc$109383$new_n15609_ ),
    .nq(\$\soc.cpu.minerva.gprf.mem._mem$rdreg[1]$d [0])
  );

There is a variable with 2 \ that seems to be causing a problem. Changing \$\soc to \$soc solves the problem. Maybe netgen does not process \ inside escaped variables (variables that start with \) correctly.

test_netgen.tgz

To reproduce:

tar xzf test_netgen.tgz
cd test_netgen
netgen -batch source lvs.script  # original file with all errors
netgen -batch source lvs.script.fix1  # attributes removed
netgen -batch source lvs.script.fix2  # attributes and double \ removed

Note: vdd and vss instance connections have been added to the original verilog files.

[RTimothyEdwards]

@d-m-bailey : Fixed in version 1.5.258.

[RTimothyEdwards]

@d-m-bailey : Thank you for the test case. It was pretty easy to track down the two places where the errors are happening.