clash-compiler
clash-compiler copied to clipboard
clash-lang
Haskell to VHDL/Verilog/SystemVerilog compiler
`Clash.Magic.clashCompileError` only works if the argument is a literal string. But sometimes I want to provide a richer error message, for example I want to write this function: ``` ascii...
We have tests that are not run for most PR's: * GitHub CI's `build_and_test` only runs for external PR's * GitLab CI contains a bunch of tests that only run...
[comment]: # (Thank you for contributing to Clash. Please fill out this template to describe your contribution and any outstanding tasks / questions.) [comment]: # (External PRs will not automatically...
`SNat` is part of `base-4.18.0.0` and later. Up to this point, we've defined our own version: ```haskell data SNat (n :: Nat) where SNat :: KnownNat n => SNat n...
From https://github.com/clash-lang/clash-compiler/pull/2738#discussion_r1676074225. The 8b/10b decoder sometimes decodes garbage as valid data. In practice this should not cause any direct issues as properly encoded data will never be improperly decoded, but...
Currently the 8b/10b line coding uses two large (1024 and 2048 entry) lookup tables. This is not efficient, and can be done in a better way. Some of the suggestions...
We have `resize`, a function that can truncate by throwing away bits. We also have `checkedResize`, a function that does the same, but throws an error in simulation if the...
See https://github.com/gergoerdi/clash-protocols-issue-93 I have this in `src/Main.hs`: ``` {-# OPTIONS -fplugin=Protocols.Plugin #-} ``` This is picked up by GHC when building simulations via Stack. But when I run Clash via...
Observed on the CI runs of https://github.com/clash-lang/clash-compiler/pull/2768, I see that running the vector testsuite takes: - On GHC 9.4: 7m19s https://github.com/clash-lang/clash-compiler/actions/runs/10091542369/job/27903324484 - On GHC 9.8: 1h32m57s https://github.com/clash-lang/clash-compiler/actions/runs/10091542369/job/27903324825
Metadata
Owner
Metadata
Haskell to VHDL/Verilog/SystemVerilog compiler