clash-compiler
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Haskell to VHDL/Verilog/SystemVerilog compiler
I was banging my head against some type errors for hours until I decided to use the `Cons` constructor instead of the `:>` pattern - hopefully this will save someone...
I've got this beauty: ```haskell debugIla :: Signal freeclk () debugIla = ila ((ilaConfig $ "ila_probe_maybeAlignedRxData0" :> "ila_probe_gtwiz_userdata_tx_in" :> "ila_probe_reset_rx_done" :> "ila_probe_reset_tx_done" :> "ila_probe_rst_all_in" :> "ila_probe_validAlign" :> "ila_probe_alignRst" :> "ila_probe_prbsErrors"...
Slow in simulation implementation: ```Haskell -- | Reverse bitvector reverseBV :: KnownNat n => BitVector n -> BitVector n reverseBV = v2bv . reverse . bv2v ``` _Originally mentioned by...
This program: ```haskell {-# LANGUAGE MagicHash #-} module Hello where import Clash.Annotations.BitRepresentation import Clash.Prelude data Animal = Turtle | Wombat | Bear deriving (Eq) {-# ANN module (DataReprAnn $(liftQ [t|Animal|])...
That is, the following causes Clash to generate one module for `bbWrapper`: ```haskell topEntity :: Vec 4 (Signal System Bit) topEntity = zipWith3 bbWrapper indicesI indicesI indicesI {-# CLASH_OPAQUE topEntity...
That is, a function `primtive` rendered in two modules `primitive.vhdl` and `primitive_0.vhdl` will generate variables `x` and `x_0` respectively when asking for `x`. While usually not impactful, primitives such as...
Same as https://github.com/clash-lang/clash-compiler/issues/2717, but for VIO
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[comment]: # (Thank you for contributing to Clash. Please fill out this template to describe your contribution and any outstanding tasks / questions.) [comment]: # (External PRs will not automatically...
An alternative means to achieve https://github.com/clash-lang/clash-compiler/pull/2734#issuecomment-2182893091 ```haskell import Clash.Prelude import Data.Proxy f :: forall dom . KnownDomain dom => Proxy dom -> SNat (PeriodToCycles dom (Milliseconds 1)) f Proxy =...