clash-compiler

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VHDL type / signal naming collisions

1

I encountered a situation where Vivado could not process my HDL because a type "A" collided with a signal name "a". GHC version: 9.0.2 Clash version: 1.6.3 Consider the following...

lmbollen

Add dynamic clock periods

4

## Still TODO: - [x] Write a changelog entry (see changelog/README.md) - [x] Check copyright notices are up to date in edited files

martijnbastiaan

Include clock origin and phase in domain.

7

In some cases a design requires clocks to be related somehow. For instance a low overhead clock crossing can be implemented if two clocks have the same origin, phase and...

rowanG077

Don't terminate Verilog simulator on error in assertion functions

9

Simulators (at least ModelSim) terminate immediately on `$finish` making it impossible to set e.g. an exit code to flag the error to the shell. I also noticed that the SystemVerilog...

acairncross

Question about the performance of the Fixed type

13

I'm implementing an FM radio receiver in clash [here](https://github.com/adamwalker/fpga-fm-radio). The [fixed point](https://hackage.haskell.org/package/clash-prelude-1.6.3/docs/Clash-Sized-Fixed.html) data types have been very useful for keeping track of the decimal point and make DSP super nice...

adamwalker

Add Xilinx dual clock FIFO primitive to `clash-cores`

20

This adds Xilinx's DcFifo to clash-cores. The Haskell model and the IP are both tested. Past discussion is [here](https://github.com/clash-lang/clash-compiler/pull/2182#issue-1222094757); it is bit cluttered. It's a draft PR because it depends...

vmchale

Netlist generation fails on `Unsigned 1`

2

After some refactoring I hit a bug where Clash failed during Normalization. When trying reducing to reduce it to a smaller case I no-longer hit a Normalization but hit a...

rowanG077

See https://github.com/martijnbastiaan/tasty/pull/2. This reduces the startup time of `clash-testsuite` from ~half a minute to sub second figures. I still have some i's to dot and t's to cross for that...

martijnbastiaan

Malformed haddock in `clash-prelude`

1

The API documentation for [`head` and `tail`](https://hackage.haskell.org/package/clash-prelude-1.6.3/docs/Clash-Sized-Vector.html#v:head) for the current stable version of Clash is slightly malformed, resulting in the documentation being rendered badly. I see: ...

alex-mckenna

generated systemverilog fails to compile with iverilog

2

I've been trying iverilog ("icarus verilog") on the system verilog code output from clash (approx 1.6.3) but it won't compile, well, parse, because .... iverilog doesn't seem to accept the...

pbreuer