rocket-chip

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Migration to new world Chisel.

9

In the Chisel 3.6, the compatibility layer of Chise2 will be finally deprecated after chipsalliance/chisel3#2668 get merged, In the open-source community, RC is obviously the biggest downstream user of this...

sequencer

Documentation for ptw and tlb

1

**Related issue**: Documentation **Type of change**: bug report | feature request | other enhancement other enhancement **Impact**: no functional change | API addition (no impact on existing code) | API...

midnighter95

Failing store conditionals bring the data to cache and mark them dirty

2

**Type of issue**: bug report **Impact**: unknown **Development Phase**: request **Other information** I noticed that in Rocket core when store conditional (sc.w) instructions execute when there is no reservation (sc...

sammy17

[mill] compile fails

1

command: mill -i rocketchip error: 35/137] rocketchip.macros.compile [info] compiling 1 Scala source to rocket-chip\out\rocketchip\macros\compile.dest\classes ... [info] done compiling [66/137] foreign-modules.hardfloat.hardfloat.compile [info] compiling 20 Scala sources to rocket-chip\out\foreign-modules\hardfloat\hardfloat\compile.dest\classes ... [error] ##...

pxs7

**Type of issue**: bug report **Impact**: unknown **Development Phase**: request **Other information** I noticed a weird behavior related to div/rem instructions in Rocket core while testing a new dynamic verification...

sammy17

icache and dcache with ECC (secded) enabled only works with zero initialized RAM arrays

2

**Type of issue**: bug report | question **Impact**: unknown Applying ECC to to icache and dcache tag and data arrays works in simulation only if the RAM arrays are initialized...

tiwdi

### Discussed in https://github.com/chipsalliance/rocket-chip/discussions/3010 I felt like the following two lines of code is redundant https://github.com/chipsalliance/rocket-chip/blob/00d9e02c1901d0285f22eefec7c25073fb90e4f1/src/main/scala/devices/debug/Debug.scala#L1782 ``` dmInner.module.clock := io.debug_clock dmInner.module.reset := io.debug_reset ``` since the clock domain of **dmInner(TLDebugModuleInner)**...

DecodeTheEncoded

[TestDriver.v] Set initial `clock = 1'b1;`

3

**Related issue**: Potential timing violation in the initial condition. **Type of change**: other enhancement **Impact**: no functional change **Development Phase**: implementation **Release Notes** Set `clock = 1'b1;` to avoid the...

Waxpple

**Related issue**: **Type of change**: bug report | feature request | other enhancement **Impact**: no functional change | API addition (no impact on existing code) | API modification **Development Phase**:...

sequencer

https://github.com/chipsalliance/rocket-chip/blob/b503f8ac28a497b2463ffbac84bfe66533ace0bb/src/main/scala/devices/debug/Periphery.scala#L115 This references a workaround for a chisel issue closed by https://github.com/chipsalliance/chisel3/pull/1660 My guess is this naming bug workaround can probably be removed now? I'll look into it later but...

michael-etzkorn