clock domain confusion on debug-related components

[DecodeTheEncoded]

Discussed in https://github.com/chipsalliance/rocket-chip/discussions/3010

I felt like the following two lines of code is redundant https://github.com/chipsalliance/rocket-chip/blob/00d9e02c1901d0285f22eefec7c25073fb90e4f1/src/main/scala/devices/debug/Debug.scala#L1782

      dmInner.module.clock := io.debug_clock
      dmInner.module.reset := io.debug_reset

since the clock domain of dmInner(TLDebugModuleInner) has already been successfully set via https://github.com/chipsalliance/rocket-chip/blob/00d9e02c1901d0285f22eefec7c25073fb90e4f1/src/main/scala/devices/debug/Debug.scala#L1777