Chris Fallin

Generally I agree at an IR-design level: it would be nice to have orthogonality here, and allow all types up through `i128` in all places where integers are allowed. This...

I just merged in `main` to this PR to see if it fixes CI.

Hmm, @bnjbvr it looks like some of the changes broke the fuzz targets -- happy to merge once that is fixed up.

I'm going to start working down the `x86_64` opcode list from the top -- clz/btz/popcnt/bitrev to start, I think. @abrown let me know what your next plans are and we...

@abrown are you still planning to take a look at stores on x64? I'm happy to take those first thing Mon if you haven't started yet, as I've got some...

@dheaton-arm I'm planning to help push the aarch64 work to completion; I'm hoping to tackle some of the trickier remaining ones (loads and stores, with amode lowering; calls; branches; icmp/fcmp...

OK great, I'll take loads/stores themselves, calls, and branches. Lowering of flags-using instructions will intersect with how we do icmp/fcmp so I'll hold off on those. Thanks! > My patch...

Put up PRs for call/ret and loads/stores today; the remaining instructions on aarch64 that don't depend on flags or pattern-matching with icmp/fcmp somehow are: - GetPinnedReg/SetPinnedReg - ExtractLane/InsertLane - StackAddr...

@dheaton-arm great! I shifted over to some regalloc semantics cleanup work but I can come back and do `br*` ops next, likely Thu or Fri, unless you want to claim...

@dheaton-arm that sounds great; I didn't get to it last week as the regalloc stuff took longer than expected. Please feel free to grab all the branch ops and let...