calyx
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calyxir
Intermediate Language (IL) for Hardware Accelerator Generators
Just found this issue out with @rachitnigam; Ports can be named `primitive` which is a reserved verilog keyword, thus leading to verilog that does not compile.
When using fud from within python via `run_fud`, fud will change the current working directory to an invalid value. Not sure exactly where this occurs, but running `getcwd()` after `run_fud`...
## Extension Much of the work on the extension is largely around ergonomics as it has some barebones functionality already. Lots of these are not mission critical - [x] Convert...
Awesome! Yeah, this is unfortunately messy and right way to fix it is to support `ref` definitions in CIRCT (https://github.com/llvm/circt/issues/4831). If this becomes a blocking problem for your use case,...
Currently `yxi` outputs only names, data width of the memory, and size of the memory in cells. We should add `IDX_SIZE` information to this as well, as this is required...
Imagine a component like: ``` component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) { cells { ... } wires { \\ 0 or more...
Currently, this is something only I do but it would be good to have a documentation page describing how to release a new version. Briefly: 1. Bump the `version` field...
Making this an issue instead of a discussion to avoid discussion blindness, but we can move that if preferred. This is based on a conversation @sampsyo and I had today....
The keyword checks need to be expanded to check components & primitives. The list itself may also need to be expanded. This comes from the discussion here: https://github.com/cucapra/calyx/discussions/1356 In the...
In exploring what kinds of programs work/don't work well on fpgas as part of going through the calyx -> FPGA flow we currently have, it was found that [xclrun.py](https://github.com/cucapra/calyx/blob/master/fud/fud/xclrun.py) does...