calebmkim

It seems like there are two main things for this. 1) The renaming of cells can no longer be arbitrary-- we would have to rename to the largest width adder....

No, the most recent PR changes LiveRangeAnalysis and MinimizeRegs so that the MinimizeRegs pass does what the previous MinimizeRegs and ResourceSharing passes both did.

Oh, sorry. But in that case again answer is no. The pass only dealt with transforming par blocks.

Once I get LiveRangeAnalysis to Handle Comb Groups, here's what I was thinking (for the ordering of the pre-opt passes). CompileInvoke is currently in compile but I have moved it...

1) LRA doesn't handle comb groups yet, although I can start working on that-- we can discuss more synchronously, but I've been thinking about it like this: for `invoke _...

So https://github.com/cucapra/calyx/pull/1144 handles this particular issue, in the sense that invokes are compiled into groups so that the `MergeStaticPar` and `StaticParConv` passes see groups. However, there may be some work...

About 1), I agree, I hadn't thought about an infinite loop and that seems more likely. For running it through the interpreter, is your idea that the interpreter would give...

So I get the following error in the interpreter when I run squeezenet: ``` Aug 29 18:20:27.983 WARN Computation over/underflow, source: main.bias_add_1x16x55x55_.add561 Aug 29 18:20:30.857 WARN Computation over/underflow, source: main.relu_1x16x55x55_.add147...

Sorry, I meant that I couldn't find exactly where the code was going wrong. It is wrong, I just can't pinpoint the exact place.

Update on the squeezenet.futil file stuff. I checked the interpreter, and the while loop with @ bound(1) actually does only run once. And the one-bit adder does what it's supposed...