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simavr is a lean, mean and hackable AVR simulator for linux & OSX

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Hi, When doing a write transaction, I'm getting the wrong status in TWSR after sending the address. I'm reading 0x28 which stands for data write w ack, I was expecting...

The directory "obj-x86_64-linux-gnu" needs to be manually created to get the examples to compile. Without it, I get this error (for i2ctest for example): `i2ctest.c:87:1: fatal error: opening dependency file...

Hi, Current SBI simulation implementation works wrong when the target is PINx register. [The code](https://github.com/buserror/simavr/blob/master/simavr/sim/sim_core.c#L1281): ```cpp case 0x9a00: { // SBI -- Set Bit in I/O Register -- 1001 1010...

Hi, the situation. A port has some pins assigned as outputs, and some as inputs. Inputs have their associated pin-change interrupts enabled. So when setting just a single output pin...

Hi there! I was wondering if the ATMega16m1 simulation has CAN support built in? So can we fake CAN messages and see how the chip will respond? I use a...

is there any way to optimize the code below? instead of registering pin by pin, monitor all? ``` // connect all the pins on port B to our callback for...

Hi, how are you First of all I would like to congratulate you on the brilliant project. I have known him for a while, before I had not been able...

Hi All, I would like to exit simAVR with a non-zero exit code, for instance if a byte in the atMega is non-zero. This would allow me to remotely run...

https://github.com/buserror/simavr/blob/master/simavr/sim/avr_uart.c#L248 Sometimes (most of the time?) there are zero parity bits but simavr assume's there's always one.