Bogdan Luncan

## PR Description This PR adds the jesd204b support for the AD9081 project on VCK190. ## PR Type - [ ] Bug fix (change that fixes an issue) - [x]...

Base design for VPK180

1

## PR Description Adds the base design for Versal Premium (VPK180). Requires Vivado 2023.2 as Vivado 2023.1 doesn't have support for this carrier. ## PR Type - [ ] Bug...

## PR Description This PR adds a configurable decimator/interpolator between the ADC and DAC paths. ## PR Type - [ ] Bug fix (change that fixes an issue) - [x]...

Added logging of make params to the sysid memory

3

Projects that can be configured using make parameters should now log their build parameters inside the sysid memory. For some projects that have a lot of parameters the sysid memory...

Agilex support for AD9081

1

## PR Description Adds support for JESD204B on Agilex 7 (DK-SI-AGI027FA) and the reference design project for AD9081. Tested on hardware with 8 lanes, 8 converters and a lane rate...

Fixed nextstable timings not met

3

## PR Description Changed implementation strategies for the projects that were failing. ## PR Type - [x] Bug fix (change that fixes an issue) - [ ] New feature (change...

## PR Description The ad_mem_hp1_interconnect for rx_dma was set to $sys_cpu_clock instead of $sys_dma_clock ## PR Type - [x] Bug fix (change that fixes an issue) - [ ] New...

Agilex: JESD204C support

1

## PR Description Adds JESD204C support for Agilex 7 I-Series (FM87) boards. It uses the Intel _F-Tile PMA and FEC Direct PHY_ IP as the physical layer alongside a custom...