Base design for VPK180

[bluncan]

PR Description

Adds the base design for Versal Premium (VPK180).

Requires Vivado 2023.2 as Vivado 2023.1 doesn't have support for this carrier.

PR Type

• [ ] Bug fix (change that fixes an issue)
• [x] New feature (change that adds new functionality)
• [ ] Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• [x] I have followed the code style guidelines
• [x] I have performed a self-review of changes
• [x] I have compiled all hdl projects and libraries affected by this PR
• [x] I have tested in hardware affected projects, at least on relevant boards
• [ ] I have commented my code, at least hard-to-understand parts
• [x] I have signed off all commits from this PR
• [x] I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• [ ] I have not introduced new Warnings/Critical Warnings on compilation
• [ ] I have added new hdl testbenches or updated existing ones

[bluncan]

v2: Changed interconnects to be one after the other and placed the interrupt after the 'interrupts' comment