Björn Quentin

Turned out clearing the interrupts earlier (which seemed to make sense) caused problems for ESP32-S3 .... Very glad we have HIL-TESTs in place

Looks nice. Given this runs a small amount of code every time allloc/dealloc is called would it make sense to have that feature gated?

> Additionally, I noticed the rv-init-data and rv-init-rtc-data features (and the esp-riscv-rt features they enable) seem to have only been used for the old direct boot support. I also attempted...

Looks quite good overall - I guess after adding a CHANGELOG.md entry this should be good to go One thing maybe worth considering would be to have a (doc-hidden) function...

Probably all the reset reasons which are chip-reset or system-reset should always trigger zeroing: (from C6 TRM)  > I wrote the condition in assembly to match the rest of...

Seems like the description in the TRM fooled me a bit and "System Reset: resets the whole digital system, including LP system." doesn't mean LP/RTC RAM is reset. So only...

t.b.h. I guess the above scenario is not completely impossible in a development setup but maybe unlikely in production - not too sure At least not zeroing on e.g. WDT...

> Update the docs to warn about the potential for resets during writes and to avoid resets immediately after first boot Yes, we probably should explain these things more >...

Looks good but I'm on vacation this week -not sure if and when I will get to this before next week. So, if anyone likes to review this: feel free

I think the traits in embedded HAL are designed in a way which makes things like these very inconvenient. That's also the reason why ADC is removed for now from...