Ben Reynwar
Ben Reynwar
Configurable Generators ======================= At the moment all the parameters for a 'generator' must be fully specified in the core file with the corresponding 'generate' (ttctg). It would be useful to...
Looks like a file is missing from the repo. ``` g++ -g -O2 test_all.cc -o test_all test_all.cc:25: fatal error: qa_rtty.h: No such file or directory ```
Implement conversion of the AST back into a VHDL text file. There are a number of possible uses for having the ability to go back from the AST to VHDL....
Currently the RTI codebase is somewhat difficult to work on because there are lots of factors (RTI node structure, context, bounds location, whether it's in a signal or generic) that...
**Description** The goal is to make it possible to use cocotb with a design that uses nested records and arrays in it's ports, signals and generics. Related to issue #237....
…compilation. I'm running verilator on a large design and the compilation was taking a long time. I wanted to able to call 'make -j 16' to speed things up, but...
The riscv-gnu-toolchain repo commit that is checked out when running `piton/ariane_build_tools.sh` (which in turn calls `piton/design/chip/tile/ariane/ci/build-riscv-gcc.sh`) is from 2017. Some git submodules don't even exist anymore. I assume that no-one...
These were the changes I needed to make to get `test_axil_crossbar.py` working with verilator, along with using cocotb-bus=0.1.1. If you think it would be useful, I can try to get...
https://github.com/mkdocs/mkdocs/blob/master/docs/getting-started.md?plain=1#L84 ``` curl 'https://jaspervdj.be/lorem-markdownum/markdown.txt' > docs/about.md ``` The content of this file looks suspicious. Probably best not to be grabbing something from a random website in the getting started tutorial.
### Dafny version 4.7.0.0 ### Code to produce this issue ```dafny lemma FailingCase1() ensures map[3 := 0].Values == {0} { } lemma PassingCase() ensures map[3 := 0].Values == {3} ensures...