http://www.reynwar.net/ben [email protected]
USC, Information Sciences Institiute Tucson, Arizona, USA Interested in the intersection of hardware design, formal methods and machine learning.
Ben Reynwar
Verilog module for calculation of FFT.
benreynwar
Verilog modules for software-defined radio.
Python tools for Vivado Projects
A parser and autocorrection tool for wiktionary.
