Bartłomiej Chmiel

Add parameterless assert control system tasks

5

The SystemVerilog language supports Assertion control system tasks (IEEE 1800-2023 20.11). Such tasks are not supported by the Verilator. This PR provides partial support for the parameterless assertion control tasks....

Thread pool rewrite

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This PR introduces a simpler approach to the implementation of `V3ThreadPool` and multi-threading in general. ## Issues with the current thread pool The current thread pool is more generic than...

Parallelize V3VariableOrder

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This PR introduces parallel variable ordering. Now variables are ordered for each `AstNodeModule` in parallel. Only `AstVar`s directly under modules are reordered so there is no interdependence between modules. On...

Add error when calling a function with :: on a non-instantiated interface

1

# The problem I get the following internal error when calling a function on a non-instantiated interface. ``` %Error: Internal Error: t/t_linkdot_bug.v:7:11: ../V3LinkDot.cpp:422: Module/etc never assigned a symbol entry? -node:...

Add binary expression type checking for arrays

1

I'd received internal errors in V3DfgPeephole regarding mismatched width of operands. Verilated using master as of https://github.com/verilator/verilator/commit/9656311521a7fe33054a4921986fa0cf8f6c0f5f. ## RHS mismatch internal error Error message: ```cpp %Error: Internal Error: t/t_dfg_peephole_bug.v:12:19: ../V3DfgPeephole.cpp:956:...

I'd received a compilation error regarding incorrectly emitted array assignment. Verilated using master as of https://github.com/verilator/verilator/commit/9656311521a7fe33054a4921986fa0cf8f6c0f5f. ## Error ```python ./Vt_emit_bug___024root__DepSet_h02b3a51b__0__Slow.cpp:97:29: error: assigning to 'CData' (aka 'unsigned char') from incompatible type...

Incorrect result for `t_func_dotted_inl0` with `--public`

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Got incorrect simulation result for the test `t_func_dotted_inl0.py` when running it with `--public`. https://github.com/verilator/verilator/blob/01157d414b56ee199d55e6eb956bf4f67c2f37e4/test_regress/t/t_func_dotted.v#L1-L159 https://github.com/verilator/verilator/blob/01157d414b56ee199d55e6eb956bf4f67c2f37e4/test_regress/t/t_func_dotted_inl0.py#L1-L38 Output with `--public`: ``` top.t.ma0.u_b[0].f top.t.ma0.u_b[0].f %Error: t/t_func_dotted.v:135: Verilog $stop Aborting... ``` Expected output: ```...

rmp: Genetic algorithm for slack tuning

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New resynthesis strategy for `rmp`. Alternative approach to https://github.com/The-OpenROAD-Project/OpenROAD/pull/8437 for optimizing ABC timing. Utilizes a genetic algorithm with the following tunable parameters: - population size - mutation probability - cross...

rmp: eqy test check

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Adds eqy check for gcd_annealing1 and gcd_annealing2 tests in rmp. As those tests require loading liberty files for eqy, changed `run_equivalence_test`'s interface to allow selecting both a library directory (for...