Ayaka Yorihiro
Ayaka Yorihiro
## Who [@5hubh4m](github.com/5hubh4m), [@ayakayorihiro](github.com/ayakayorihiro), and [@anshumanmohan](github.com/anshumanmohan) ## What We will implement an LLVM frontend for a small but useful programming language. The choices we are considering are: - `awk`, which...
Branching off of #1603 - one blocker for deprecating `@external` and adopting `ref`'s synthesis mode everywhere is that currently the version of Verilog generated by synthesis mode (externalizing all memories)...
This issue lists out the next steps for implementing and testing a Calyx-to-FIRRTL backend, as described in #1552 . Current status: I added `fud2` support for the FIRRTL backend! -...
This issue lists out steps for profiling! (Mostly so I can organize my TODOs.) Will update as I move along. ### Inspections & QoL improvements to profiler - Running the...
This PR contains small revisions to profiling: 1. We now show a summary for each group before showing the complete information. 2. We now use the corresponding TDCC group's `go`...
This PR contains some small follow-ons to the FIRRTL backend: - We now use [firtool](https://github.com/llvm/circt/releases/tag/firtool-1.75.0) instead of the deprecated FIRRTL compiler in fud2 (thanks @ekiwi!). Note that I changed fud2's...
This is a tracking issue for an effort to switch Calyx's testbenching. ## Background Currently, all Calyx-compiled Verilog programs use the same [standalone testbench](https://github.com/calyxir/calyx/blob/main/fud2/rsrc/tb.sv). The downside of this setup is...