asky26
asky26
1.2.1 I use function to cal the port width.
// code begin module top_module#(parameter in_w = 1)( input in, output out ); parameter out_w = do_math(in_w); wire [out_w-1 : 0] out; function output_width; input input_width; begin do_math = input_width...
Sorry for my mistake. Here is the code that I have run with the iverilog. ////////////// module top_module#(parameter in_w = 1)( input in, output [out_w-1 : 0] out ); localparam...
I have test the code with version 1.3.0. Insert comand: `python .\examples\example_dataflow_analyzer.py -t top_module .\my_code\top_module.v` But I got this: pyverilog.utils.verror.FormatError: unsupported AST node type: output_width Can you fix it? or...
Maybe function can be processed in 2 ways. 1) Fcuntion is called in module, just as the example. The best way should analyize the function code, and get the return...
Where should I add my code if I want to deal with verilog module which contain the function. I found the the it failed at "visit.py". I want to try...
I have make some local modification. And I got this:  It works, with some wrong infomation. I am not totally understand source code. Can I get some deltailed instructions?