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function in module can not be parse, and get error

Open asky26 opened this issue 4 years ago • 13 comments

Test the module which contain the funtion code in it, then I got error. I check the code of lex. It has the key word "function". So I guess that I have to modify yacc to make it work well.

I already have run the pyverilog well with some simple verilog code which do not have function in it.

asky26 avatar Jan 10 '21 14:01 asky26

Which version?

shtaxxx avatar Jan 10 '21 15:01 shtaxxx

1.2.1 I use function to cal the port width.

asky26 avatar Jan 10 '21 15:01 asky26

Can you show your code?

shtaxxx avatar Jan 10 '21 15:01 shtaxxx

// code begin module top_module#(parameter in_w = 1)( input in, output out ); parameter out_w = do_math(in_w); wire [out_w-1 : 0] out; function output_width; input input_width; begin do_math = input_width + 1; end endfunction assign out = in + 1; endmodule // code end

I do not have the code rigth now. It is hard to copy code from my computer for the work. So I write the simple code manually.

asky26 avatar Jan 10 '21 15:01 asky26

module top_module#(parameter in_w = 1)( input in, output out );
parameter out_w = do_math(in_w);
wire [out_w-1 : 0] out;
function output_width;
input input_width;
begin
do_math = input_width + 1;
end
endfunction
assign out = in + 1;
endmodule

Before testing your code on Pyverilog 1.2.1, I passed your code to Icarus Verilog, and it says the code has an error.

iverilog -tnull -Wall test.v
test.v:2: error: No function named `do_math' found in this context (top_module).
1 error(s) during elaboration.

shtaxxx avatar Jan 10 '21 16:01 shtaxxx

Sorry for my mistake. Here is the code that I have run with the iverilog. ////////////// module top_module#(parameter in_w = 1)( input in, output [out_w-1 : 0] out ); localparam out_w = output_width(in_w);

function integer output_width;
	input input_width;
begin
	output_width = input_width + 1;
end

endfunction assign out = in + 1; endmodule

asky26 avatar Jan 11 '21 15:01 asky26

I have test the code with version 1.3.0. Insert comand: python .\examples\example_dataflow_analyzer.py -t top_module .\my_code\top_module.v But I got this: pyverilog.utils.verror.FormatError: unsupported AST node type: <class 'pyverilog.vparser.ast.FunctionCall'> output_width

Can you fix it? or is there a way to skip this error.

asky26 avatar Jan 21 '21 14:01 asky26

 python3 example_parser.py ~/tmp/yourcode.v
Generating LALR tables
WARNING: 183 shift/reduce conflicts
Source:  (at 1)
  Description:  (at 1)
    ModuleDef: top_module (at 1)
      Paramlist:  (at 1)
        Decl:  (at 1)
          Parameter: in_w, False (at 1)
            Rvalue:  (at 1)
              IntConst: 1 (at 1)
      Portlist:  (at 1)
        Ioport:  (at 2)
          Input: in, False (at 2)
        Ioport:  (at 3)
          Output: out, False (at 3)
            Width:  (at 3)
              Minus:  (at 3)
                Identifier: out_w (at 3)
                IntConst: 1 (at 3)
              IntConst: 0 (at 3)
      Decl:  (at 4)
        Localparam: out_w, False (at 4)
          Rvalue:  (at 4)
            FunctionCall:  (at 4)
              Identifier: output_width (at 4)
              Identifier: in_w (at 4)
      Function: output_width (at 6)
        Width:  (at 6)
          IntConst: 31 (at 6)
          IntConst: 0 (at 6)
        Decl:  (at 7)
          Input: input_width, False (at 7)
        Block: None (at 8)
          BlockingSubstitution:  (at 9)
            Lvalue:  (at 9)
              Identifier: output_width (at 9)
            Rvalue:  (at 9)
              Plus:  (at 9)
                Identifier: input_width (at 9)
                IntConst: 1 (at 9)
      Assign:  (at 12)
        Lvalue:  (at 12)
          Identifier: out (at 12)
        Rvalue:  (at 12)
          Plus:  (at 12)
            Identifier: in (at 12)
            IntConst: 1 (at 12)

There is no error in parsing.

As you pointed out, dataflow analyzer might have no rules for function integer funcname.

Do you need the dataflow analyzer? I am very appreciated if you suggest how to modify the dataflow analyzer.

shtaxxx avatar Jan 21 '21 14:01 shtaxxx

Maybe function can be processed in 2 ways.

  1. Fcuntion is called in module, just as the example. The best way should analyize the function code, and get the return value of the function called. But it seems like a hard way. In actually, function code is not my key point, but some modules in filelist have function in themself, so the dataflow-analyzer can not keey going. Maybe set some options for me, to make dataflow analyzer skip the function. For example, leave the the code that the function is called. The most verilog-code do not have the function. I want to use dataflow analyzer to make some rule check.
  2. Fucntion is used for simulation. It can be skiped, I guess

Thank you for your help.

asky26 avatar Jan 27 '21 14:01 asky26

Where should I add my code if I want to deal with verilog module which contain the function. I found the the it failed at "visit.py". I want to try to fix it. Could you please suggest?

asky26 avatar Mar 15 '21 15:03 asky26

I have make some local modification. And I got this: image It works, with some wrong infomation. I am not totally understand source code. Can I get some deltailed instructions?

asky26 avatar May 04 '21 14:05 asky26

function in module can not be parse, and get error image

How do I handle this error?

This is my function image

INSIinc avatar Sep 27 '21 15:09 INSIinc

Test the module which contain the funtion code Parser in it, then I got error. and it is not parsing I am using version 1.3

File "C:\Users\alfredMoussa\Anaconda3\lib\site-packages\pyverilog\vparser\parser.py", line 2340, in parse ast = codeparser.parse()

File "C:\Users\alfredMoussa\Anaconda3\lib\site-packages\pyverilog\vparser\parser.py", line 2317, in parse text = self.preprocess()

File "C:\Users\alfredMoussa\Anaconda3\lib\site-packages\pyverilog\vparser\parser.py", line 2310, in preprocess text = open(self.preprocess_output).read()

FileNotFoundError: [Errno 2] No such file or directory: 'preprocess.output'

vivoo94 avatar Oct 02 '22 19:10 vivoo94