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function in module can not be parse, and get error
Test the module which contain the funtion code in it, then I got error. I check the code of lex. It has the key word "function". So I guess that I have to modify yacc to make it work well.
I already have run the pyverilog well with some simple verilog code which do not have function in it.
Which version?
1.2.1 I use function to cal the port width.
Can you show your code?
// code begin module top_module#(parameter in_w = 1)( input in, output out ); parameter out_w = do_math(in_w); wire [out_w-1 : 0] out; function output_width; input input_width; begin do_math = input_width + 1; end endfunction assign out = in + 1; endmodule // code end
I do not have the code rigth now. It is hard to copy code from my computer for the work. So I write the simple code manually.
module top_module#(parameter in_w = 1)( input in, output out );
parameter out_w = do_math(in_w);
wire [out_w-1 : 0] out;
function output_width;
input input_width;
begin
do_math = input_width + 1;
end
endfunction
assign out = in + 1;
endmodule
Before testing your code on Pyverilog 1.2.1, I passed your code to Icarus Verilog, and it says the code has an error.
iverilog -tnull -Wall test.v
test.v:2: error: No function named `do_math' found in this context (top_module).
1 error(s) during elaboration.
Sorry for my mistake. Here is the code that I have run with the iverilog. ////////////// module top_module#(parameter in_w = 1)( input in, output [out_w-1 : 0] out ); localparam out_w = output_width(in_w);
function integer output_width;
input input_width;
begin
output_width = input_width + 1;
end
endfunction assign out = in + 1; endmodule
I have test the code with version 1.3.0.
Insert comand:
python .\examples\example_dataflow_analyzer.py -t top_module .\my_code\top_module.v
But I got this:
pyverilog.utils.verror.FormatError: unsupported AST node type: <class 'pyverilog.vparser.ast.FunctionCall'> output_width
Can you fix it? or is there a way to skip this error.
python3 example_parser.py ~/tmp/yourcode.v
Generating LALR tables
WARNING: 183 shift/reduce conflicts
Source: (at 1)
Description: (at 1)
ModuleDef: top_module (at 1)
Paramlist: (at 1)
Decl: (at 1)
Parameter: in_w, False (at 1)
Rvalue: (at 1)
IntConst: 1 (at 1)
Portlist: (at 1)
Ioport: (at 2)
Input: in, False (at 2)
Ioport: (at 3)
Output: out, False (at 3)
Width: (at 3)
Minus: (at 3)
Identifier: out_w (at 3)
IntConst: 1 (at 3)
IntConst: 0 (at 3)
Decl: (at 4)
Localparam: out_w, False (at 4)
Rvalue: (at 4)
FunctionCall: (at 4)
Identifier: output_width (at 4)
Identifier: in_w (at 4)
Function: output_width (at 6)
Width: (at 6)
IntConst: 31 (at 6)
IntConst: 0 (at 6)
Decl: (at 7)
Input: input_width, False (at 7)
Block: None (at 8)
BlockingSubstitution: (at 9)
Lvalue: (at 9)
Identifier: output_width (at 9)
Rvalue: (at 9)
Plus: (at 9)
Identifier: input_width (at 9)
IntConst: 1 (at 9)
Assign: (at 12)
Lvalue: (at 12)
Identifier: out (at 12)
Rvalue: (at 12)
Plus: (at 12)
Identifier: in (at 12)
IntConst: 1 (at 12)
There is no error in parsing.
As you pointed out, dataflow analyzer might have no rules for function integer funcname
.
Do you need the dataflow analyzer? I am very appreciated if you suggest how to modify the dataflow analyzer.
Maybe function can be processed in 2 ways.
- Fcuntion is called in module, just as the example. The best way should analyize the function code, and get the return value of the function called. But it seems like a hard way. In actually, function code is not my key point, but some modules in filelist have function in themself, so the dataflow-analyzer can not keey going. Maybe set some options for me, to make dataflow analyzer skip the function. For example, leave the the code that the function is called. The most verilog-code do not have the function. I want to use dataflow analyzer to make some rule check.
- Fucntion is used for simulation. It can be skiped, I guess
Thank you for your help.
Where should I add my code if I want to deal with verilog module which contain the function. I found the the it failed at "visit.py". I want to try to fix it. Could you please suggest?
I have make some local modification. And I got this:
It works, with some wrong infomation.
I am not totally understand source code. Can I get some deltailed instructions?
function in module can not be parse, and get error
How do I handle this error?
This is my function
Test the module which contain the funtion code Parser in it, then I got error. and it is not parsing I am using version 1.3
File "C:\Users\alfredMoussa\Anaconda3\lib\site-packages\pyverilog\vparser\parser.py", line 2340, in parse ast = codeparser.parse()
File "C:\Users\alfredMoussa\Anaconda3\lib\site-packages\pyverilog\vparser\parser.py", line 2317, in parse text = self.preprocess()
File "C:\Users\alfredMoussa\Anaconda3\lib\site-packages\pyverilog\vparser\parser.py", line 2310, in preprocess text = open(self.preprocess_output).read()
FileNotFoundError: [Errno 2] No such file or directory: 'preprocess.output'