Anton Blanchard

Pass Core config parameters via Makefile

1

Instead of hardwiring the parameters in Core.scala, pass them in via the Makefile. It makes configuration much easier. Signed-off-by: Anton Blanchard

Signed-off-by: Anton Blanchard

loadMemoryFromFile() should place readmemh() inline for better compatibility

18

`loadMemoryFromFile()` creates a separate file and uses a SV bind statement. A simple example: ``` import chisel3._ import chisel3.util.experimental.loadMemoryFromFile class Foo(val bits: Int, val size: Int, filename: String) extends Module...

Thin areas of sky130 met1 rails have no tap cells

13

I wanted to see how OpenROAD handles very small areas between the perimeter of the core area and placed macros. I took a working design (40um macro halo with the...

@jjcherry95 pointed out some issues with default SDC file in Openlane, so I thought I'd go through all the timing settings: - `set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks $::env(CLOCK_PORT)]` The comment on this...

Add clock tree metal layer constraints

1

@jjcherry56 points out that Openlane is not constraining the clock tree metal layers. Depending on the process, we might want to use upper/larger metal layers. We need a few changes:...

Add OpenROAD remove_buffers to flow

2

@jjcherry56 points out that we should have the option of calling `remove_buffers` before we call `repair_design`, to undo any buffer addition that yosys/abc does. To complicate matters, Openlane currently has...

Issues with buffer selection

3

In https://github.com/efabless/caravel/issues/41 @rtimothyedwards mentions: > It is also unclear to me why openlane uses "clkbuf" buffers for input buffering. There is no particular need for an oversized balanced > buffer...

CTS post processing makes clock skew significantly worse

2

I'm noticing high clock skew on some `sky130hd` designs. While trying to narrow this down, I found that adding `-post_cts_disable` helps a lot: ``` baseline (cts.tcl): Clock ext_clk Latency CRPR...

How to resolve large differences between placement parasitics and global route parasitics

15

I'm trying to improve the frequency of my gate level multiplier when taping out on ASAP7. The slowest path after global routing was not the slowest path before global routing,...