Andrei Warkentin

Tiano components cannot depend on GPL/LGPL components. An alternative UC implementation could be done with box64 or DynamoRio.

According to the ISA doc, "Instruction-address-misaligned exceptions are not possible on machines that support extensions with 16-bit aligned instructions, such as the compressed instruction-set extension, C.". See page 21 of...

In short, it's easy to add EXCEPT_RISCV_INST_MISALIGNED handling, but impossible to test it, short of hacking together a custom qemu/sbi/edk2 build to target rv64g instead of rv64gc. Will skip this,...

ASWG Mantis 2407 does this already (https://mantis.uefi.org/mantis/view.php?id=2407): "On Intel and RISC-V platforms, if the \_CCA object is not supplied, the OSPM will assume the devices are hardware cache coherent." Once...

As far as collecting the data, there are many ways this could be done. The most obvious one would be "collecting at compile time", as the hart register state is...

> Compiling the information into the firmware would imply a new firmware for every new mimpid (I would assume that matches a CPU stepping). It's highly likely stepping differences will...

I'm not sure any of the above discussion is useful in practice in a guidance document. If you feel like it is, please work on a pull request. If not,...

To paraphrase the Arm BBRS (https://developer.arm.com/documentation/den0107/latest/) Platform requirements for BRS-based systems that enable standard, suitably built operating systems to seamlessly use standard security interfaces. These interfaces include the following security...

Need to revisit this, esp wrt https://github.com/riscv-non-isa/riscv-brs/issues/136 and https://github.com/riscv-non-isa/riscv-brs/issues/135

" no direct access from OS to hardware" seems out of scope... better to be in server-platform spec... in fact this is the SEC_020 requirement.