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Published 20 hours ago • verified publisher icon intel

MAU_TRY_WITHOUT_MMU: should this handle EXCEPT_RISCV_INST_MISALIGNED?

Open andreiw opened this issue 2 years ago • 2 comments

I've never seen this in the wild, but I suppose it is possible.

andreiw avatar Dec 10 '23 07:12 andreiw

According to the ISA doc, "Instruction-address-misaligned exceptions are not possible on machines that support extensions with 16-bit aligned instructions, such as the compressed instruction-set extension, C.". See page 21 of 20191213.

andreiw avatar Dec 12 '23 02:12 andreiw

In short, it's easy to add EXCEPT_RISCV_INST_MISALIGNED handling, but impossible to test it, short of hacking together a custom qemu/sbi/edk2 build to target rv64g instead of rv64gc. Will skip this, esp. given the corner case (not running with an MMU, which is an unsupported scenario anyway).

andreiw avatar Dec 12 '23 02:12 andreiw