verilog-i2c
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alexforencich
Verilog I2C interface for FPGA implementation
I'm trying to test what happens when I issue a read to a slave address that doesn't exists. I expect the core to send out the start bit, the address,...
Some I2C devices support reading multiple data bytes from a register which contains more than one byte of data. Current implantation only supports a single byte read. Example device is...
When simulating the i2c master module under verilator, several linting errors occurred that this commit addresses. Specifically * Several types were of excessive length and were subject to vector length...
I tried to use i2c_master_axil.v on Vivado, but it seems like there is a problem I could't figure its reason... When try to read or write from MIcroBlaze CPU to...
I wanted to be able to discover if a slave was available on the bus by using a ping. Basically a ping will only send the address, and then the...
There seems to be an issue that only shows itself if the write-through fifo for data is disabled. The **data_in_valid_int** net seems to be dangling w/o a driver and thus...
To when has a brupt release bus or sop condition and the bus don't stop because the slave.
1. separated phy from master, 2. added 'tb' just for phy 3. formatted everything with verible-verilog-format 4. testing rtl/ -i2c_master.v -i2c_slave.v -i2c_single_reg.v with iverilog and verilator, it works `verilator -y...
Hi Alex, we implemented and used this i2c-mux in some of our designs. For now the testbench is just hard-coded as we have no experience with myhdl and needed to...
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Verilog I2C interface for FPGA implementation