i2c_master.v: Stop after nack from slave

[vanjoe]

I'm trying to test what happens when I issue a read to a slave address that doesn't exists. I expect the core to send out the start bit, the address, the read bit, then receive a nack back, then send out a stop bit.

But from STATE_ADDRESS_2 which is where the missed_ack_next is set, there is no way to got to STATE_STOP . I am looking at https://github.com/alexforencich/verilog-i2c/blob/e7a26811e71de2bfa25ba704a1031c2bff9e5c31/rtl/i2c_master.v#L504

Am I missing something?