SureLog - UHDM

the file external/basejump_stl/bsg_misc/bsg_counter_up_down.variable.v does not exit instead external/basejump_stl/bsg_misc/bsg_counter_up_down_variable.v exists. Yet somehow the command line given to surelog contains the typo ("." instead of "_").

BlackParrot has such example: third_party/cores/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_int_alu.v Either add -sverilog (to treat all files as SystemVerilog) or prefix particular files with -sv option, like: -sv third_party/cores/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_int_alu.v

BlackParrot Verilog vs SystemVerilog files

3

I logged the following issue on BlackParrot, but I want to make sure sv-tests does the right thing when creating the project file. On SV-Tests, I have the following error...