agozillon
agozillon
The cl::sycl::vec class appears to double in size for whatever type and element number it contains. For example a cl::sycl::vec is not 16 bytes its 32 bytes and a cl::sycl::vec...
This is a non-exhaustive list of some larger problems relating to XIlinx FPGA compilation and runtime execution (some with more information than others) that need some thought long term: -----------...
I'm not sure how interested you'd (@keryell) be in changing this, but I thought I'd open up an issue in any case as a general reminder that it can be...
Some math manglings from xocc's SPIR libraries appear to be incorrect or missing. In the sense that math functions correctly translated to their SPIR mangled names (found in: https://github.com/KhronosGroup/SPIR-Tools/wiki/SPIR-2.0-built-in-functions) result...
As an extension to https://github.com/triSYCL/sycl/issues/9 there are currently some incorrectly mangled SPIR builtins in POCL (https://github.com/pocl/pocl/issues/698) that will need to be handled for clean execution of SYCL spir-df output by...
The following tests have difficulty compiling for hw_emu in SDAccel 2019.1.1 at the moment: vector_math.cpp (ICE in xocc: "Bitcode for HLS" pass) edge_detection.cpp (ICE in xocc: 'Function Pass Manager' and...
Things like XILINX_XRT which are set by the user and others like XILINX_DEVICE_ONLY that are set by the compiler but affect the code users compile may be useful to add.
Currently `parallel_for_workgroup` is implemented for intel devices, but will not work on Xilinx devices. It should hopefully be a very easy fix, but it's low priority for us at the...
It should be very simple to add support for POCL. Our kernels are already SPIR-df when we feed our FPGA target through. We just have some slight strangeness that we...
Perhaps worth delaying this for a while until we have use cases for it, as the upstream driver isn't cemented and ours works "fine" for the moment. But there is...