Alessandro Comodi

I see that [CHANGELOG.md](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/doc/src/CHANGELOG.md) in `doc/src` is actually a symlink to the actual CHANGELOG.md in the root dir, while for the other `.md` files (e.g. `CONTRIBUTING.md`), there is no symlink...

Hi @ethanroj23, so, to test on either the 100T or 200T you'd need to use the following files from the corresponding tarballs: - `arch.timing.xml` - `rr_graph_.lookahead.bin` - `rr_graph_.place_delay.bin` - `rr_graph_.rr_graph.real.bin`...

I think the solution should be the one proposed in https://github.com/capnproto/capnproto/issues/1370#issuecomment-953067555. The issue we had were mainly related to the reading limit which, IIRC, can be pushed up to `2**63`,...

Hi @gergoerdi, inserting a BUFG at the `25MHZ` clock should solve the problem. e.g.: ```verilog MMCM_25 u_MMCM_25 (.CLKIN_100MHZ(CLK100MHZ), .CLKOUT_25MHZ(CLK_25MHZ), .LOCKED(CLK_LOCKED) ); wire CLK_25MHZ_BUFG; BUFG BUFG(.I(CLK_25MHZ), .O(CLK_25MHZ_BUFG)); topEntity u_topEntity (.CLK_25MHZ(CLK_25MHZ_BUFG), ......

I think that we may leave this open and close it until whichever one of the following is done: - enable automatic yosys inference of clock buffers (currently disabled here...

@litghost @HackerFoo FYI, I have started the work to get an updated yosys version on master+wip. To reproduce the tests I have been performing these are the branches and commits...

Update: > SRL post-synthesis testbenches fail This seems indeed to be related to ABC9. By disabling abc9, all the post-synthesis tests do pass. I believe that we could remove the...

Update on Ethernet not working on the Linux-capable litex design. I have come across a few things that might be helpful to get forward in the debug process: - FDSE...

Opened the issue upstream: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1379. I added a fix locally, I need to add a basic regression test and I'll open a PR soon.

@smunaut I opened a PR with a fix that should solve the problem opened here: https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1380