Yuan-Mao

Hi I have a question about the axi_lite_from_mem module: https://github.com/pulp-platform/axi/blob/master/src/axi_lite_from_mem.sv#L176 Looks like the module uses a FIFO to track the read/write order of all incoming transactions and asserts bready and...

Linux Device Driver Support

9

Hi, Is there any Linux driver support for your Ethernet MAC? Thanks!

ASIC implementation for verilog-ethernet

5

Hi, To my understanding, this repo is now currently only for FPGA implementation, so I wonder if your team plans to target any ASIC implementation in the near future? Or...

Question about ASYNC_REG

6

Hi, I am learning about how to set Vivado properties properly for CDC. When I looked down into the module 'axis_async_fifo', I didn't see any (* ASYNC_REG = "TRUE" *)...

Questions about Clock Domain Crossing in axis_async_fifo

1

Hi I am looking at this specific commit 40acee1bc59c8091c65cedfa470cc16cbce8e6bb. The module "axis_async_fifo" has a write clock domain (driven by s_clk) and a read clock domain (driven by m_clk). To my...