Will Green

I've dusted off my ULX3S board and have successfully built the first few of your versions. I think the best way to handle this is to take each _FPGA Graphics_...

Agreed with @tristanitschner to close this PR. There is a new PR #128 covering FPGA Graphics.

Hello, Thank you for adding MIF support to img2fmem. Could you update `img2fmem/README.md` to include basic info on MIF support and how to run your test? TIA, Will

I'm seeing this same issue with the current version of Canvas LMS on Ubuntu 20.04. I'm using the system provided Ruby 2.7 installed with apt. I can also confirm I...

I've spotted another anomaly with division: ```python from FixedPoint import FXfamily, FXnum fp_family = FXfamily(n_bits=4, n_intbits=5) # five integer bits as answer is >8 x = fp_family(1.375) y = fp_family(0.125)...

Thank you for the quick response. I'm using Python and your module to validate the fixed-point division logic in my FPGA design. I'm worked around this issue by doing the...

I've settled on [Gaussian rounding](https://en.wikipedia.org/wiki/Rounding#Rounding_half_to_even) (round to even). It's slightly more complex to implement, but matches the default in Python and IEEE 745 (floating point standard). You can see my...

Thanks for the quick reply. I fixed the problem by putting the `dep` folder in the same folder as BitsNPicas.jar and running: ```shell java -cp dep -jar BitsNPicas.jar ``` It...

This was fixed by PR #129 in November 2022. The blog was updated in October 2022: https://projectf.io/posts/lib-clock-xd/

Hello @goekce, In the last couple of months, I've published a revised intro to numbers and a separate draft post covering vectors: * https://projectf.io/posts/numbers-in-verilog/ * https://projectf.io/posts/verilog-vectors-arrays/ I hope these revised...