FPGA-ftdi245fifo

FPGA-ftdi245fifo copied to clipboard

Problem with FT232H : 32bits TX (fpga--> PC) 16 upper bits with 16 lower bits switched sometimes after a cold start

5

Hi, I copy-past the verilog code inside my fpga. For info i use one UM232H board (FT232H chip) connected with one Digilent CMOD Board (fpga xilinx artix7). 8bits and 16bits...

collins4you

Does this code require custom programming of the FT232H's EEPROM, e.g. via the FTDI prog program, or can it work with new stock FT232 as is? The reason I ask...

zapta

I have this core implemented in a Zynq with a DMA implemented to send and receive data from the FTDI core which is connected to an FT601. However, sending data...

gswdh

回环收发数据不一致

2

大佬，你好，我用了你的IP和顶层loopback，硬件上使用以FT232h为核心的CJMCU-232H模块,和xilinx的spartan-6 开发板（黑金AX309），用usb_loopback_simple.py发送16字节时收发数据是一致的，但是在usb_loopback_mass.py里连续收发数据会出现不一致的情况，（txdata and rxdata mismatch）, 想问一下会是什么原因呢

shdzjk

Probable issue fix when sending more than 512 bytes

8

Hello @WangXuan95 and thanks for this IP, it saves me a lot of time. I've ported your code to Verilog. I'm working on a ECP5 Lattice, running at synchronous mode...

lk-davidegironi

The D3XX DLL seems to freeze when calling readPipe() after having already called readPipe() with return status timeout error. The timeout happens because usb_loopback_simple.py attempts to receive twice as many...

PatrickJohnDavies

Hello, It will be helpful update the usb_rx_mass program in Python to verify the data read on a host match the data generated by the FPGA logic ? Currently, it...

jinz2014