Implemented design on a Zynq no PC -> FPGA communication

[gswdh]

I have this core implemented in a Zynq with a DMA implemented to send and receive data from the FTDI core which is connected to an FT601. However, sending data from the PC to the FPGA does not work, FPGA -> PC does work.

I have tested my DMA on the Zynq via a loop back - working great.

A loop back with or without a FIFO on the IP core does not work.

With the DMA connected to the IP core does not work.

I did have to manually implement two of the parameters as follows due to synth error in Vivado.

localparam  CHIP_EW               = 2;
localparam  CHIP_DRIVE_AT_NEGEDGE = 0;

The project I have it implemented in is in this project https://github.com/gswdh/CameraFPGA/tree/develop

I wonder if there's any advice or example project of implementing this core on a Xilinx device.