Tim Hutt
Tim Hutt
Oh actually it turns out type level if-then-else was only added to Sail three weeks ago! Very timely. But it means we'll need to wait for the next Sail release...
Hmm that is a good point. Unfortunately I don't think Sail supports type level enums so supporting multiple 16-bit float formats in this way is going to be a bit...
Closing this since we can use the code included in Sail instead.
Good call, that does sound better and I guess would let you treat other exceptions in the same way (I'll have to double check the code though). I don't think...
I agree we need a proper interface for this. Currently the only option is the RVFI code. We have hackily commented all that out and replaced it with our own...
That is how we currently record CSR accesses but I think the "list of events" approach is likely worse than function callbacks. 1. Lists are an endangered Sail feature. They...
The SystemVerilog support is very experimental. I really doubt it would work with the whole RISC-V model. I think the thing you've hit is that it doesn't support lists. IIRC...
Ah maybe. It's in the 20211203 version (current ratified one linked [from the risc-v website](https://riscv.org/technical/specifications/)).
Yeah see #319. I would suggest that until we have flags for this it probably makes sense to implement the latest ratified version and add comments where there are differences...
Ah this is very timely, because I just fixed a bug where I mixed up physical and virtual addresses and was just thinking "if only I could do `newtype physaddr...