Tim Hutt
Tim Hutt
I think we're talking about different things. Implementations are allowed to do the actual memory writes (*after* PMP checks) separately, but they can't do independent PMP checks for each part...
Oh yeah you're right... I should have read slightly further! > Note that a single instruction may generate multiple accesses, which may not be mutually atomic. An access-fault exception is...
I think this is a duplicate of #184
> Maybe the way to go would be to add a CSR attribute to the appropriate registers, then have Sail insert the logging statements. Would perhaps be less error prone...
We're using this for model checking - not coverage - so it needs to exactly match what our DUT says. When you write to `sstatus` the instrumentation of our DUT...
Hmm I suppose there are two similar but subtly different things you might want to know: * What are the changes to the underlying architectural state? (`mstatus` changed) * What...
Actually it's worse than I thought; it also *writes* 8 bytes for Sv32 when updating the accessed/dirty bits. This pretty much means Sv32 is broken at the moment.
> Are you planning on making a separate PR for the writes, or adjust this one? I'll update this one.
Ok I updated it to include the writes too. I am also working on refactoring the virtual memory code to use Sail's type system properly in all of this code,...
Note, not all instances of this can be replaced by `range()`. Any where the type variable appears more than once, or has some maths done to it (usually `8 *...