Thomasb81

I am looking at that, but I am confuse because preprocessor result is different from what I would have expect. include.vh ``` input a, //`include "include2.vh" output c ``` test.v...

unfortunately no progress.

There is no python API to handle preprocessor stuff. As for C or C++, verilog standard suggests to manage preprocessor directive before building model throught compilation and elaboration phase. Your...

Usually user don't like to read generated code. It end up to be very repetitive, with no so interesting comments inside. Base of this observation you could just print the...

What you request is non conform to verilog and systemVerilog standard. I cannot confirm your claim see my log produced by Cadence, Mentor/Siemens and Synopsys. [dc_shell.log](https://github.com/Nic30/hdlConvertor/files/7610199/dc_shell.log) [xrun.log](https://github.com/Nic30/hdlConvertor/files/7610203/xrun.log) [questa.log](https://github.com/Nic30/hdlConvertor/files/7610207/questa.log) None of...

The interest of scikit-build/cmake was the compatibility with antlr4 build system and cython/python. January 2022 it will be 2 years since python2.7 is end of life... It's probably time to...

I guess contribution are welcome. Basically : implement antlr visitePackage_declaration method and other visit* method relevant for your application in cpp. Fill structure with data you want to collect and...

I don't think so. That's why the tool can emit such message : "Source_textParser.visitDescription.package_declaration Conversion to Python object not implemented" at some place to point the limitation.

My interest is code analyze to extract what is useful and interesting for IP reuse and verification. Now it's open source project. If someone find useful to build on top...

Did we miss some` fork / join `construction syntax ?