hdlConvertor
hdlConvertor copied to clipboard
Nic30
incorrect Position
Hello
Position return by the tool is incorrect: include.vh:
input a
test.v:
module my_module(
`include "include.vh"
);
endmodule
test.py
from hdlConvertorAst.language import Language
from hdlConvertor import HdlConvertor
c = HdlConvertor()
d = c.parse("test.v", Language.VERILOG, [])
print(d.objs[0])
Return
...
'ports': [{'__class__': 'HdlIdDef',
'direction': 'IN',
'name': {'__class__': 'str', 'val': 'a'},
'position': (5, 1, 5, 7),
'type': 'wire'}],
...
5 refer to post processed source code which make no sens for an user. We expect here an information as " include.vh, start_line 1, start_position 1,end_line 1, end_position 7"
I am looking at that, but I am confuse because preprocessor result is different from what I would have expect. include.vh
input a,
//`include "include2.vh"
output c
test.v
module my_module(
`include "include.vh"
);
endmodule
is translate into
module my_module(
input a,
//`include "include2.vh"
output c
);
endmodule
Newline have been inserted .
The data are coherent but this is making thing difficult to understand. Especially if we want to extend the mechanic to provide to the parser the ability to take into account some positional compîler directive timescale default_nettype pragma ... that can take different value in a source code and impact differently the model to be build.
Hello @Thomasb81 , have you had any success fixing this issue? In next week I still do not have any time, but I think that this fix is something essential and simply must be done. It is required to reuse the information about origin of the line, which should be already present. It was left unfinished, because there was the question if we should change API to provide whole hierarchy of files and lines as they were added using include.
@Thomasb81 , theoretically I do have some people through summer jobs, I do not know if it is withing their reach but I hopefully the branch with the fix will be finally finished and merged.