Thomasb81

@hs-apotell could you disclose your file or reproduce a testcase that you can attach to a new issue ? We did your best to test all syntax that are depict...

@Nic30 It is not so clear to me. By the past the big 3 simulator had some divergence of behavior on the same SV code. It is still possible that...

> I have an alternative to this (parse includes, use hdlconvertor on the included files, then remove the results from the main HdlContext), but having a way to do it...

I guess https://github.com/Nic30/hdlConvertor/issues/88 and https://github.com/Nic30/hdlConvertor/issues/89 are the same. If not, you should provide example, otherwise we won't understand each other. What you complain is that the original position of the...

Patch and tests are welcome.

I understand that the 2 first bullets are working together. But your last bullet seems to be an alternative proposition. Which is not very clear to me: How do you...

Well, it is sometime use full to dump prepossessed code. Having `line directive in this dump should allow tool interoperability... I mean reprocess the dump by another tool.

https://github.com/Nic30/hdlConvertor/blob/2d3458d0881483a0be7ff9a2b9628398ff211ee6/hdlConvertor/_hdlConvertor.pyx#L42 To be replace by ` cdef cppclass Convertor nogil:` Should do the job. (Not tested)

Those message come directly from antlr. For the first one the tool provide you the list of expect token allowed instead of ')'. For the second one the tool go...

I can agree with that, unfortunately today there is not yet the same weight of user needing open source C and C++ compiler than SystemVerilog so such day can take...