SpinalHDL

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set rst name for default clock domain by ClockDomainConfig

3

I have to name rst signal to `rst_n` instead of `resetn`

yportne13

[feature request] Option to use SystemVerilog unpacked arrays for `Vec`s in IO ports

4

Although SpinalHDL `Vec`s work well for interfacing between SpinalHDL components, they produce a bunch of named ports in Verilog modules, which can make it really tedious to interoperate with existing...

thajohns

file miss

2

Hello！ Did some files or dirs dont commit？ https://github.com/SpinalHDL/SpinalHDL/blob/2a34c667e8b72568a8b6c25f4a926863b8e068ed/sim/src/test/scala/spinal/sim/TestVCS.scala#L21 when run TestVCS1 error like this： ``` Exception in thread "main" java.io.FileNotFoundException: simulation_plugins/SharedMemIface.cpp (没有那个文件或目录) ```

ICJJ

Observations about AFix

3

I'm currently working on a project involving a lot of fixed-point math, and I noticed a few things that annoyed me about the `AFix` API that I wanted to share....

thajohns

`PackedBundle` inside `Union`?

13

Following #1337, `PackedBundle` seems like a perfect candidate to define external instruction words with holes inside the definition. However, I'm not sure how I can fit them inside a `Union`....

KireinaHoro

# Introduce Current DDRx SDRAM universal controllers for SpinalHDL do not support memory module and manufacturer coupling In order to solve the problem of tightness, we design DDRx SDRAM universal...

liyaohou

[Lint issue] Spyglass report lint issue for generated verilog code.

1

For following generated verilog code, spyglass has lint issue: > Bit-width mismatch in signal assignment (LHS: 'io_c' width 4 should match RHS: '(io_a >>> 3'd4)' width 8). [Hierarchy: ':Demo'] verilog...

facebreeze

# Context, Motivation & Description generate more meaningful & understandable signal name in fsm # Impact on code generation Only signal name changed, behaviour unchanged. # Checklist - [ ]...

Konecho

Verilog of blackbox with inout mapped to tristate port renaming issue

3

I'm trying to simulate an SPI flash with a verilog model. The blackbox definition is ```scala private[spi] final class MX25U25645G extends BlackBox { val io = new Bundle { val...

louiecaulfield

When making a `master port TriStateArray()` and obtaining an element using it's `apply()`, the `isMasterInterface` won't return correctly: ```scala val io = new Bundle { ... val data = master...

louiecaulfield