SpinalHDL
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SpinalHDL
Scala based HDL
Hello! While writing multi-clock domain code, I discovered that referencing clock domains can cause changes in the interface names of identical components. SpinalHDL mistakenly treats these components as different modules...
Closes #1310 # Context, Motivation & Description Fix wishbone pipelined mode # Impact on code generation None # Checklist - [x ] Unit tests were added - [ x] API...
This draft PR is intended more as a discussion point; I don't think it can be merged as is. # Context, Motivation & Description I'm working on a slave design...
I have a StreamMonitor Written by myself,the core function is running this function by fork: ``` while (true) { log.info(s"bus_valid:${bus.valid.toBoolean}\tbus_ready:${bus.ready.toBoolean}") if (busValidPtr.toBoolean/*.manager.getLong(busValidPtr.signal)!=0*/) { active.set() if (busReadyPtr.toBoolean/*.manager.getLong(busReadyPtr.signal)!=0*/) { recv(sample()) } }...
Spinal version: v1.10.1 Simulation tool: Synopsys VCS 2018 Here's the simulation code: ```scala SimTimeout(500 ms) val perpPort = dut.socInst.logicMainInst.coreInst.io.d_perp val coreCd = ClockDomain(dut.socInst.logicMainInst.smuInst.io.coreClkRst.clk) InitBase.doInit(dut, 10 MHz, "00".asBin) infoMonitor(perpPort, coreCd) var...
I understand that for Mem, a readWrite port can always host a read or a write port, so in principle the RAM with 1 readSync and 1 readWrite port should...
I'm trying out the plugin framework and encountered some deadlock issue: ```scala import spinal.core._ import spinal.core.fiber.Handle import spinal.lib._ import spinal.lib.misc.plugin._ class Plugin1 extends FiberPlugin { val logic = during setup...
In SpinalSim we now have the capability to interact with buses like AXI to read bits from the design. My design currently exposes some SpinalHDL `Bundle`, `Union` and `SpinalEnum` over...
I've tested xilinx IPs like multiplier, complex multiplier, divider and FFT in spinal-sim using XSim, most of them work just fine. But complex multiplier and FFT seems not working properly....
AMBA5 CHI could be a good choice for high performance cache-coherent NOC design. However, it is kind of complex. How about building a NOC library with AMBA5 CHI? We can...
