SpinalHDL
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SpinalHDL
Scala based HDL
Closes # # Context, Motivation & Description Assign some uninterested bits to zeros or ones is quite common in engineering. # Impact on code generation None # Checklist - [...
in spinal..lib.fsm how can i get the current state and nextstate ?and how can i get the statecode? for exmaple, if i got a signal named out,the out shoule be...
The combinational logic generated by Spinal (as shown in line 377 of the figure below) fails to pull the w_ready signal high when printing with Verdi, but the VCS simulation...
Example as following, ``` case class clkDemo(CK: ClockDomain = ClockDomain.current) extends Component { CK.clock.setName("CK") // **position 2** : clock rename in a component val io = new Bundle { val...
SpinalHDL 1.12.0 There are 2 examples with the SAME function. Eg1. is error and eg2 is OK. This is eg1. ``` case class clkDemo() extends Component { val io =...
I'm running the latest dev build: **commit 9fc35a953e6ea43343a27a477805a8031dec5f3d (HEAD -> dev, origin/dev, origin/HEAD)** I just switched back to VHDL rendering to run a sim in GHDL, and I get compile...
Hi SpinalHDL Developers, I propose enhancing the `report` function to include source location (file path and line number) in its output. **Motivation** Modern IDEs allow clicking terminal logs to jump...
So mostly, this PR avoid the verilog backend form emiting very large cases as : ```verilog always @(*) begin frontend_checksumIp_push = 1'b0; (* parallel_case *) case(1) // synthesis parallel_case (frontend_stateReg[frontend_INIT_OH_ID])...
The current StreamWidthAdapter only supports operations with integer multiples. I hope to add support for non-integer multiple bit-width conversions, such as converting from 12 bits to 8 bits. For example,...
I recently opened #1719 and SpinalHDL/SpinalDoc-RTD#277 to improve the doc. This issue is here to document the things still to do I have discovered so I don't forget about them....
