Himal Subedi

compiling verilog code in verilator by Verilator 4.216 2021-12-05 rev v4.216

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while compiling verilog code ( .v), i get following errors.. can you please tell me where is error either of generated code from scala to verilog (by sbt "runMain vexriscv.demo.Murax"...

Dear Charles, Is it how L1 cache and CPU communicate during Load/store ? **Pipeline: FetchCachePlugin** **Pipeline: DataCachePlugin**

 https://github.com/SpinalHDL/NaxRiscv/blob/throttle_l2/src/main/scala/naxriscv/platform/litex/NaxSoc.scala#L76 Dear charles, If I understand correctly, I've managed to derive a diagram from the provided code. I'm curious about how Memfilter communicates with L2 cache, specifically, the interfaces...

L1/L2 cache and integration with CPU pipeline

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Hi charles, I have some doubt regarding L1 and L2 cache sets and cache line in each set of L1 and L2 data cache. can you please help me to...

cache_throttling && dirty evicts counting.

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Hi charles, I was try to measure L2 cache WB counter for that i change the following but my counter gives me **22 times more** than your counter **L2 WB...

cache WB (Writeback) counter increment when reading cache line and D refill counter when writing into cache line

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Hi Charles, when performing **reading** operations during the **simulation** and **on FPGA**, `SCOPE_HART_DCACHE_WRITEBACK` counter value is increased, which was not expected. #define SCOPE_HART_DCACHE_WRITEBACK(hart) ((hart) * 0x80 + 0x14) // Read...

Drawing the cache architecture

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Hi charles, I am wondering about drawing the diagram of a cache architecture for my own purpose. Could you please let me know how it is organized? 1. L1 cache...

L2 cache writeback Counter of specific core

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Hi As 1 miss => 1 refill (for the current config), i am wondering how to measure L2 cache **Write Back(WB)** of **specific cpu core**? i am wondering how to...

threshold of maxiumum count of Naxcore that can be possible to simulate ?

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Do i have to update in following code of **naxRiscv/ext/NaxSoftware/baremetal/socdemo/crt.s** if i need multicore refill and writeback value instead of multiplying with **""0*0x80""** #define SCOPE_HART0 (SCOPE + 0*0x80) Do i...

L1 & L2 cache memory architecture of Nax core

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Dear Charles, I'd like to know how the Nax core's L1 & L2 cache memory architecture is organized, though L1 is an inclusive cache of the L2 cache. Is L2...