Arjan Bink

[XIF] Interrupts cleared too late

4

If an interrupt is cleared via a (non-bufferable) store, then the interrupt on irq_i will go low in the cycle after the store instruction left the WB stage. As the...

LIB dependency should be removed for: - 0.5.0 exception codes (LIB.7 == 1 && LIB.1 == 1) - https://github.com/openhwgroup/cv32e40s/issues/235 - 0.5.0 NMI behavior (LIB.7 == 1 && LIB.2 == 1)...

CV32E40X only See https://github.com/openhwgroup/cv32e40x/pull/633

Implement WARL bitfields in standard manner

1

Following does not follow our WARL spec: - mtvec_n.mode = csr_mtvec_init_i ? mtvec_q.mode : {1'b0, csr_wdata_int[0]}; Need to define uniform approach for implementing WARL behavior that allows for easy diffing...

Update according to https://github.com/openhwgroup/cv32e40x/pull/628

I would like to understand https://github.com/openhwgroup/cv32e40x/pull/612 better as I would prefer to undo all of its changes. Some todos related to that pull request might already have been added: -...

[XIF] Too many instructions can execute after interrupt becomes pending and enabled

7

Version 1.12 of the Privileged Spec states: > After execution of each instruction in program order, if the conditions > for an interrupt trap are true, the trap occurs immediately,...

mscratchcswl and mscratchcsw should operate on mscratch

3

mscratchcswl and mscratchcsw are currently implemented as regular CSRs and not according to the pseudo code stated in the CLIC specification. Take https://github.com/riscv/riscv-fast-interrupt/pull/241 into account as well.

Example: In the current documentation it is not clear enough when the initial value is applied for mtvec.

Take MRET debug exception from WB

2

In https://github.com/openhwgroup/cv32e40x/pull/456 an RVFI fix was done that likely could better have been done in the RTL instead. Fix that should be undone in RVFI: assign pc_mux_exception = (ctrl_fsm_i.pc_mux ==...