Arjan Bink

@Imperas The changelist is autogenerated and can therefore contain comments that do not actually apply to the specific core itself. Such non-applicable content does not impact (and is not visible...

@eroom1966 Can this ticket be closed now?

There are more CSRs missing that are already in the user manual. Let's first add the couple of remaining to be implemented CSRs in the RTL and then update the...

Rename scontext -> mscontext in following files: - bhv/include/cv32e40s_wrapper.vh - bhv/cv32e40s_rvfi.sv - bhv/include/cv32e40s_rvfi_pkg.sv

@silabs-oysteink Has this been fixed now including the mentioned issue 241?

@silabs-oysteink Should be a SEC clean change to get it fixed then; I will add it in the coming sprint.

@michael-platzer Could you give an example where you get a deadlock. Currently these flops get reset when something leaves the EX stage (or EX gets killed), which is similar (but...

See clarifications at https://github.com/riscv/riscv-debug-spec/issues/753

Our interpretation of the CLIC specin above issue description is not correct. The xinhv bit of the previous privilege mode should be used. Re-reading the 0.9-draft spec the spec is...

Please have a look at the comments I left in https://github.com/openhwgroup/cv32e40x/pull/660. It seems there are three bugs: - Not using inhv bsaed on previous privilege - Mixing ID stage and...