Arjan Bink

Hi Haugoug, Thank you for bringing up the topic of stack overflow checking and for proposing a solution for that. We also think that stack overflow checking would be a...

Hi Haugoug, as you requested I moved the stack overflow checking enhancement request (aimed at silicon as opposed to simulation-only) into a separate ticket https://github.com/pulp-platform/riscv/issues/183, so you can further ignore...

@zorrolee777 We do not have the intention to provide synthesis scripts for specific vendors, just example constraints. (I don't know if the stated issue has been fixed; I do not...

The issue has been solved except for the PMP file. PMP is however not used in CV32E40P, but file itself is kept. Once we start on a core using the...

- ISS/RTL debug: Need a well defined interface between ISS and RTL that both sides can work towards. The current method of probing directly into the RTL is relatively error...

Transferred to core-v-verif

Hi, I only read the 'issue' interface part of the vplan and here is my feedback. Following checks need to be added: - id needs to be unique (rules with...

Hi @ZElkacimi , Thank you for your response. >> transaction what do you mean by this point? @Silabs-ArjanB You can ignore that line (was a typo). >>concerning both manners of...

>> dm_exception_addr_i[31:0], which is a primary input to the core, which is currently hardwired to 0x0 in the MCU (link). That is not correct; it should point to the appropriate...

Hi @datum-dpoulin I see in above 'completion criteria' that the intention is to support all OBI signals. For the CV32E40X and CV32E40S the OBI specification has recently been extended with...