Arjan Bink

Our preference would be to use IP-XACT.

Note: This discussion is continued in https://mattermost.openhwgroup.org/all-users/channels/twg--cores--manifest

Note: This discussion is continued in https://mattermost.openhwgroup.org/all-users/channels/twg--cores--manifest

Likely the issue has been resolved by now; casex was added and removed again because of explicit CSR address encoding in https://github.com/openhwgroup/cv32e40p/pull/376. Needs to be checked though before closing this...

@strichmo @eroom1966 Hi Steve, please correct me if I am wrong here or if you have other expectations from us. The way I read above issue is that you are...

Hi @eroom1966 Can you just try 'make' instead of 'makecv32'?

Hi @eroom1966 @strichmo Is this issue still being looked at or has it been solved?

[hwloop_assertion.vcd.gz](https://github.com/openhwgroup/cv32e40p/files/5571998/hwloop_assertion.vcd.gz)

I looked at this simulation and this seems like an ISS (or tracer) issue to me. The RTL is simply honoring the debug request after the dret completes (but dret...

Hi @eroom1966 @strichmo Is this issue still being looked at or has it been solved?