Arjan Bink

Yes, just a screenshot of the relevant signals as a reminder to myself

@davidmallasen Are you blocked by this?

Note that https://github.com/openhwgroup/cv32e40x/pull/825 was closed but its proposed fix has not been merged yet

I strongly disagree with this. Use of SystemVerilog interfaces should actually be encouraged for certain uses (including this one). Removing myself from this issue.

Hi @MikeOpenHWGroup >> can you provide a specific example of where/how SV Interfaces can be safely used in RTL? https://github.com/openhwgroup/cv32e40x/blob/master/rtl/cv32e40x_core.sv >> I will reiterate that the OpenHW Cores Task Group...

>> @Silabs-ArjanB, can you share whatever synthesis guidelines your team uses to avoid these pitfalls? I can't share internal rules and guidelines

Note that https://github.com/openhwgroup/cv32e40x/pull/825 was closed but its proposed fix has not been merged yet

Hi @cnokes14 Thank you very much for your further analysis and proposed fix. After my initial pos, based on running your testbench ourselves we had found the same out-of-bounds issue...

Hi @cnokes14 , thank you for your detailed report. The cyclic path you report cannot be as stated as the execute stage does not control wb_ready_o (wb_ready comes from the...

Hi @cnokes14 (Apart from the out of bound indexing) do you still think there is a cyclic path? (I got an email with more detailed signals but I don't see...