Arjan Bink

Thank you for your answers. Agreed that 'that a correct implementation of the unprivileged architecture technically doesn't require M-mode at all'. This is why I added the phrase 'while still...

What would the impact of the presence of Zicount or Zfinx be on the MISA CSR? how can I detect that Zicount has been implemented? How can I detect that...

Thank you for the fast answer. I will start following that configuration-structure TG then.

Hi, could the CI be started again please?

Hi @bluewww Do you agree that because of the following code in dm_csrs.sv: ``` sbcs_d.sbaccess128 = 1'b0; sbcs_d.sbaccess64 = logic'(BusWidth == 32'd64); sbcs_d.sbaccess32 = logic'(BusWidth == 32'd32); sbcs_d.sbaccess16 = 1'b0;...

Alternatively the debug module could support all access sizes up to its bus width in which case byte enables can be used to implement narrow accesses on a wider bus....

@jm4rtin I stuck to the originally supported access sizes. Adding the others is not too much work either, but my main concern was to just get this bug fixed.

> > > @Silabs-ArjanB I think the best way is we enable byte and halfword accesses like you suggested: > > ``` > sbcs_d.sbaccess16 = 1'b1; > sbcs_d.sbaccess8 = 1'b1;...

Hi @noytzach How about reads, did you implement the shift for that as well (or is that already in the RTL)?

Thanks @noytzach