Saad Khalid

Hi @AleksandarKostovic , I am having same issue while synthesizing my design on Yosys. Changed the instance name as same as submodule name but still getting this error `ERROR: Module...

Never mind. Just figured it out. Included file in project, now it works.

@Superstite i think it was resolved by including that file (the module of which is instantiated) in top file. `include "your_file_name.v"

running spike in interactive debug mode might help - https://github.com/riscv-software-src/riscv-isa-sim#interactive-debug-mode

Hi @alexmikhalevich , there are some hypervisor tests available under this repo - https://github.com/josecm/riscv-hyp-tests although i have not tried those, but they seem pretty comprehensive.