Rot127

@chiffreKing Can you provide me with a list of instructions which have the incorrect access flags? I would fix them manually and they can be part of the `v5.0.2` release....

Closed by https://github.com/capstone-engine/capstone/pull/2400

Unfortunately, the RISCV module is still not updated and is at the level of LLVM 7. This is likely why it isn't decoding it. Checkout https://github.com/capstone-engine/capstone/issues/2015 for any progress in...

Can you ping me in the [Telegram channel](https://t.me/CapstoneEngine) of Capstone, please?

If you can't use Telegram I would write something properly out for RISCV, but it will take a day or two.

@trojanwarriors There is the idea to generate the RISCV module not from LLVM, but use [SAIL](https://github.com/riscv/sail-riscv). Because the definitions have way better quality. So please ping us before starting to...

Thanks a lot for the detailed issue! Currently I am updating to [LLVM 18](https://github.com/capstone-engine/llvm-capstone/pull/45) and will add your fix after it. Couldn't find the time yet to address the other...

@FinnWilkinson I am currently at this. Thanks for spotting the faulty regex. It is fixed now. Regarding the representation of SME operands. What do you think about having two types...

This is now the resulting output: ``` cstool -d aarch64 c0089fe04131a2e067447125 0 c0 08 9f e0 ld1w {za0h.s[w12, 0]}, p2/z, [x6] ID: 474 (ld1w) Is alias: 1466 (ld1w) with ALIAS...

> A possible solution could be to add a variable to cs_aarch_op called index which any operand can have: The thing is that these indices differ quite a lot (the...