Raphael Klink

sims -sys=manycore -novcs_build -midas_only -midas_args="-DUART_DIV_LATCH=0x36 -DFPGA_HW -DCIOP -DNO_SLAN_INIT_SPC" dhrystone.c -ariane -uart_dmw -x_tiles=1 -y_tiles=1 sims: ==================================================== sims: Simulation Script for OpenPiton sims: Modified by Princeton University on June 9th, 2015 sims:...

Hello I double checked the steps you mentioned and it seems that the benchmarks are well compiled and I already found the executables where they should be. ![Screenshot from 2021-01-15...

I am on the newest commit of the development branch. I have tried the .riscv as well as the .c When i put the .c file it get this output...

I tried it with -precompiled and --precompiled and it failed both times with the same error

yes that was the error thank you for your help. And apparently i am not on the dev branch for some reason when i checkout the dev branch out, i...

Yes, thank you, that fixed the problem. I had changed the block.list, but not the Xilinx IPs. I had thought, they would be recreated automatically with the new values. Unfortunately...

What do you mean with the frequency changes? I lowered the resistors to 100 Ohm, only then the clock was halfway decent (checked with an osciloscop) and it detected the...

Hey, for our FPGA implementation we use the Digital Top and these 3 Files *.top.mems.v *.top.v plusarg_reader.v When you want to use the Chiptop you need the 3 verilog files...

Oh yes my bad. I did not use this repository. I use Chipyard (https://github.com/ucb-bar/chipyard). This is also from UCB and uses Rocketchip as the base for a whole SoC. The...

There is another option you could try. I was unfortunaly not able you get this option running on an VCU108 Board. The ethernet is split in two parts: MAC (Media...