Pietro Ghiglio

Unable to reconstruct for loop in lambda function

3

Hello, I noticed that the CanonicalizeFor pass is unable to reconstruct the for loop from this code: ``` struct A{ int end; int step; A(int end, int step) : end(end),...

[SYCL] [NATIVECPU] Integrate OneAPI Construction Kit vectorizer

3

This PR enables Whole Function Vectorization for the Native CPU backend by integrating the OneAPI Construction Kit's vectorizer.

Enables using the oneAPI Construction Kit for SYCL Native CPU in the linux build jobs.

[SYCL] [NATIVECPU] Implement generic atomic store for generic target

1

Implements `__spirv_AtomicStore` similarly to https://github.com/intel/llvm/pull/13249. Note that the `IMPL` macro has been extended to take in a `SUB` parameter, similarly to what happens for [amdgcn](https://github.com/intel/llvm/blob/a5a0e1296269195de90949537597b2788bb5e836/libclc/amdgcn-amdhsa/libspirv/atomic/atomic_store.cl#L13) and [ptx](https://github.com/intel/llvm/blob/a5a0e1296269195de90949537597b2788bb5e836/libclc/ptx-nvidiacl/libspirv/atomic/atomic_store.cl#L39).

Currently building Native CPU with shared libraries enabled leads to a CMake error when configuring: some components of the oneAPI Construction Kit depend on `LLVMPasses`, and since they are also...

This PR implements missing builtins for `half` for the `generic` target and the missing overloads of `popcount` for `x86_64-unknown-linux`. The accompanying UR change (https://github.com/oneapi-src/unified-runtime/pull/1628) reports `cl_khr_fp16` as supported, allowing us...

Testing PR for https://github.com/oneapi-src/unified-runtime/pull/1618.

[NATIVECPU] Fix coverity warnings when handling reqd_work_group_size

2

This PR fixes some new coverity warnings reported in the Native CPU adapter: * `mdNode` is defined with `const auto&` to avoid copies * hProgram uses `unique_ptr` to avoid leaks...

Reports `cl_khr_fp16` as supported on Native CPU. Corresponding UR PR: https://github.com/intel/llvm/pull/13829

Currently the Native CPU backend implements only `UR_MEMORY_ORDER_CAPABILITY_FLAG_RELAXED`, but the adapter reports all the memory order capabilities. This PR addressed it by reporting only `UR_MEMORY_ORDER_CAPABILITY_FLAG_RELAXED`. intel/llvm PR: https://github.com/intel/llvm/pull/13469 This makes...